Seraph said:
Firstly, the D flip flop stores 1 bit right?
Yes.
Seraph said:
for it to actually store a bit of data , does the clock Input have to be set to 1 at the beginning...?
This depends on the type of D flip flop. What kind of D FF are you looking at? Edge triggered D FFs only store the value in the input on a clock transition. Negative edge triggered FFs store the value on a falling clock edge, and positive edge triggered FFs store on the rising clock edge.
Seraph said:
however... the RS flip-flop stores 1 bit as well? Whats going on here? whats the major difference here between the two circuits im really confused at the complement Of Q as well , sure it serves as an input value in the Flip Flop but other than that , what is its purpose?
The RS (or SR) FF and the D FF both store 1 bit (there are many types of FFs, like JK and T FFs that all one bit). But the difference lies in the
way that it is stored. Most types of FFs all have their kind of flaws - and depending on the application, one type of FF might not be suited to it's job because its flaw.
Lets look at the RS flip flop. Do you understand the concept of the master and slave in the RS flip flop? If not, don't read on.
A flaw the master slave SR FF can best be explained by a scenario. First lets look at the typical operation:
1) A high clock signal enters the master of the SR FF. As a consequence, the master latch reads its input, and latches onto this value.
2) The clock becomes low, the inverter driving the clock signal of the slave turns the slave latch on, and it reads the value on the master's output, latching on to it.
3) The information is stored.
Now, lets consider this scenario:
1) A high clock signal enters the master of the SR FF. As a consequence, the master latch reads its input.
During the high of the clock cycle, the input goes high, and the master latch latches onto this value. But, during this same high clock cycle, the input goes low again. But it is already too late, the master latch has already latched on to the first high signal
2) The clock becomes low, the inverter driving the clock signal of the slave turns the slave latch on, and it reads the value on the master's output, latching on to it.
3) The (wrong) information is stored.
The net effect that in the second scenario should give a low output in the SR FF because during that one high clock cycle, the input went low, but the master latch already mistakenly latched the high value, and as a result passed this mistake down to the slave latch.
How can this problem be solved? Using a D FF.
The D FF, unlike the SR FF, is
edge triggered, which means it only reads input on a rising or falling clock edge (unlike the SR FF which read input as long as the clock was high, resulting in it not reading anymore values once the master latched once). The edge trigger property of the D FF means even if an input changes during a clock cycle, it doesn't matter since the D FF
only considered the value at the clock edge.
Seraph said:
im really confused at the complement Of Q as well , sure it serves as an input value in the Flip Flop but other than that , what is its purpose?
Q and Qbar? These are outputs! Q is what you would expect your output to be. Qbar is the negation of Q, which in most cases is just a by product of the FF/latch circuit itself, which is sometimes useful.
Hope that helps.
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